In the drive to unlock cost savings in the manufacture of silicon carbide (SiC) power devices, much attention is given to substrate supply and their underlying costs, automated 200 mm foundries, and the move towards trench device architectures. Yet, the biggest challenge (and cost) in the fabrication and design of a SiC MOSFET is its oldest: how to form a high quality and reliable dielectric layer (oxide) on the SiC surface, or – if failing that – how to live with an imperfect oxide through processing workarounds, device design, and testing.
Thought to be one of the biggest advantages of SiC as a wide bandgap semiconductor, just like silicon, SiC can be oxidised to form silicon dioxide (SiO2). However, the carbon content of SiC has long been known to convolute the simple oxidation process. With carbon getting stuck both within the oxide and at the interface between the oxide and SiC, this imperfect oxide has to be managed with a nitric oxide anneal to deliver an oxide good enough for the mass market.
This seemingly benign gate oxide is the root cause of so many SiC innovations. Trench device architectures overcome a high channel resistance caused by the gate oxide. As many as 25% of gate oxides fail immediately after fabrication, a major problem for device yield and cost, and an issue that necessitates a burn-in testing stage to identify the rogue devices. Meanwhile, device designers must protect a SiC MOSFET’s gate oxide at all costs to ensure longer-term reliability, which dictates device design choices and often necessitates derating.
In this first article of two about the SiC gate oxide, we begin with the origin of the problem, the carbon that is not fully removed in the oxidation of SiC and its impact on efficiency, yield and reliability. We assess the current state-of-the-art in nitrogen-based processing techniques that have helped deliver today’s transformative SiC product range.
In a second article, to be released next month, we shall consider the wider implications of the challenging gate oxide. We shall consider the current methods device manufacturers use to manage this issue in their device designs, before reviewing some of the more radical alternatives being explored in research labs to replace, or enhance, the SiC oxide.
Background – silicon carbide and its similarity to silicon
The silicon carbide (SiC) industry is now a $2bn/year market, a meteoric rise since the release of the first SiC MOSFET in 2011 and driven by demand from the electric vehicle, industrial machine, datacentre and renewable energy sectors. This success originates from the material’s fundamental properties, including its high critical electric field, high thermal conductivity and wider bandgap. These properties combine to produce the fast switching and high efficiency power converters, for which SiC has become known. Yet most of these properties are also shared by other wide bandgap semiconductors including gallium nitride, diamond and gallium oxide.
What sets apart SiC from these other wide bandgap materials is its similarity to silicon (Si) in two essential ways. First, just like Si, it is possible to grow high quality, large area boules (cylinders) of SiC that can be cut into individual freestanding substrates, on which the fabrication process can begin. These remain very expensive due to limited achievable SiC boule heights, slow growth times, and large equipment and maintenance costs. However, the industry-wide, multi-billion dollar transition from a technology based on 150 mm diameter substrates, to one based on 200 mm substrates, is one of the major sources of future projected cost reduction.
The second parallel between SiC and Si is that it is possible to form a layer of silicon dioxide (SiO2) on each of their surfaces in a process known as thermal oxidation. Owing to the fact that SiC is 50% silicon, heating its surface at temperatures between 1200-1400°C in oxygen results in the formation of SiO2, which is the perfect insulator with which to form a functioning, reliable, metal-oxide-semiconductor field-effect transistor (MOSFET).
These parallels explain the fact that SiC power devices (MOSFETs, Schottky diodes, JFETs) are near carbon copies of the Si devices developed more than half a century earlier. Indeed, cut open a 200 V Si MOSFET and compare it to a 1200V SiC MOSFET, and one would be hard pressed to spot the difference.
However, there is a more detailed story to tell regarding SiC and its oxide. For all the benefits derived from it being a compound with 50% silicon content, the role its carbon plays in the oxidation process is the root cause of longstanding limitations related to device yield, reliability, and efficiency. Indeed, the challenge of optimising the interface between SiC and SiO2 to minimise losses and improve reliability, has been the subject of hundreds of PhD theses over more than three decades.
The SiC oxidation process
Shown in Figure 1, is the SiC thermal oxidation process that occurs in a tube furnace as oxygen is passed over substrates of SiC, at temperatures of 1100-1400°C. This starts with a simple chemical reaction, oxygen binding with Si from the SiC surface to form the first SiO2 monolayers. Meanwhile, the carbon will itself react with the oxygen, forming carbon monoxide (CO), which is removed as a byproduct. Following the growth of this initial layer, the incoming oxygen permeates the thin SiO2 layer already formed, further Si from the SiC is consumed to form a deeper, thicker layer of SiO2, and most of the carbon makes it back through the thin SiO2 layer to be removed.
However, within just a few monolayers of SiO2 growth, there is evidence of trace carbon that does not depart through the SiO2. Instead, as shown in Figure 1, unreacted carbon atoms get stuck at the interface between the SiC and the newly formed SiO2. This interfacial carbon causes significant problems, as we shall later see, but at this stage the interface is still in motion, as more SiC is consumed in the on-going oxidation process. As a result, carbon that may have been released at the interface is itself consumed within the expanding oxide, where it will remain.
Once the thermal oxidation process is complete and a layer of perhaps 40 nanometres of SiO2 is formed on the SiC surface, it is not the pure SiO2 one would expect from silicon device processing. Instead, there is unwanted carbon throughout the oxide and at the now-permanent SiO2-SiC interface.
The trapped carbon problem
The MOS interface, now featuring our newly formed SiO2 gate oxide, is critical to the operation of a MOSFET transistor, and the trapped carbon has a profoundly negative effect in three key areas, related to efficiency, reliability and yield. In this section and next we shall concentrate on the efficiency issues, and the current nitrogen-based solution.
Depicted in Figure 2, the “channel” is a region that forms within just the top few nanometres of the SiC on the application of a gate voltage. This region plays the pivotal role in the operation of a MOSFET in 1) allowing a flow of charge (electrons) through the device when it is on, in 2) blocking this current when it is off, and in 3) efficiently and reliably transitioning between these states. During the “on” state, electrons pass through this narrow channel in intimate contact with the oxide interface, making its quality of critical importance.
Never one to pass up a helpful water analogy, this semiconductor-based channel can be likened to water passing through a canal or stream. The impact of the carbon that resides at our interface can be likened to several thousand boulders (or shopping trolleys) thrown into our canal, which will slow down the stream of water passing by. Similarly, the flow of electrons beneath the gate oxide is impeded by the trapped carbon. However, this is not just a physical barrier from the interfacial carbon. Each atom of unwanted, trapped carbon at – or near – the interface will have some electrical charge, which will exert a force on the stream of electrons passing beneath, as depicted in Figure 2. Referred to as interface and near-interface traps, the greater the density of unwanted carbon throughout the oxide, the slower the electron flow and, ultimately, the higher the MOSFET’s resistance.
The flow of electrons in a semiconductor is measured using a term called electron mobility. The electron mobility in the channel of a silicon MOSFET is typically greater than 400 cm2/v.s. In SiC, the trapped charge means that its electron mobility can be as low as 5 cm2/v.s. This 80× reduction in mobility results in an 80× times increase in resistance in the channel region, thereby limiting device efficiency. Indeed, channel mobilities this low could not have delivered the efficient SiC devices of today.
Today’s state of the art: Nitrogen to the rescue
The issues of the SiC gate oxide have been known since the demonstration of the first SiC MOSFETs in the early 1990s. As a result, PhD students and research scientists have investigated a vast array of potential solutions to reduce carbon trapping, increase channel mobility, and lower the device resistance. Investigations seeking to boost the channel mobility have focussed on different deposition methods, dielectric materials, SiC polytypes, crystal planes, substrate off-cut angles, and the role of material defects. More than anything else, however, many studies have considered the effect of introducing other elements into the oxidation process, including sodium, phosphorous, boron, arsenic, antimony, caesium, and others. While some of these studies resulted in high channel mobilities of >100 cm2/V.s, unintended consequences, related to yield or reliability stood in the way.
The most successful solution, by far, resulting from this body of work is the utilisation of nitrogen in the oxidation process. This involves either, the direct oxidation of SiC in nitric oxide (NO) rather than oxygen, or by carrying out a conventional oxidation in O2 and then performing a post-oxidation anneal in NO. The direct oxidation in NO results in the highest mobility, yet it is slower, meaning manufacturers typically favour the post oxidation anneal. In either case, the effect of the nitrogen is that it bonds to “dangling” (unattached) silicon at the interface, reducing the amount of charge at the interface. This typically boosts the mobility to 25-35 cm2/v.s.
The NO post-oxidation anneal has become a standard for device manufacturers, as this mobility value is just high enough to be viable. As we will see in Part 2 on this subject, from modelling we have carried out, in a state of the art, 750V SiC MOSFET, the channel accounts for 10-20% of the total device resistance, depending on the design. Yet, the SiC channel mobility remains an order of magnitude lower than the equivalent silicon value. Our modelling, suggests that an improvement to around 100 cm2/v.s will all but eliminate this resistance.
Improving channel mobility is a key driver for resistance reductions and efficiency gains that itself ultimately leads to die shrink and yield improvement. However, this is only one aspect of the gate oxide problem, which also affects long-term reliability and production yield.
Oxide-related MOSFET reliability
The use of nitrogen-based post-deposition anneals within the oxidation process is an effective process that has been successfully transferred to the industrial environment, but it cannot entirely heal the imperfect oxide formed on SiC. As previously mentioned, carbon remains throughout the entire oxide, not just at the interface, resulting in fixed and mobile charge states in the oxide itself. This has a major impact on the working of a MOSFET, leading to various reliability challenges.
One of these challenges is a long-term vulnerability to failure if the oxide is exposed to too much stress over too long a time period. This drives two important factors in the device design, a need to produce designs that “protect” the gate oxide from high electric fields within the device, and the derating of the device – the utilisation of conservative device design (which ultimately reduces efficiency) to limit stress.
Several other quirks of using this oxide exist, including the fact that its threshold voltage (the gate voltage required to turn on the device) can drift up or down in voltage as a result of applying a voltage to the gate. In circumstances where devices are connected in parallel with others to increase current throughput (i.e. automotive applications), if this is unchecked, unmatched threshold voltages can lead to uneven wear and ultimately premature device failure.
Progress in these areas has been rapid over the last few years, and these issues are under control. Successful mitigation strategies, including derating, means that threshold voltage instability is not a major issue today when devices are utilised within the safe conditions specified on an automotive-qualified MOSFET datasheet. However, as we will see in Part 2, the limitations imposed to achieve this are restrictive.
Oxide-related MOSFET yield issues
One of the biggest challenges for chip manufacturers is that gate oxide failures are the largest source of yield loss in the device fabrication process, eclipsing failures that originate from substrate defects. For some manufacturers, as many as 25% of fabricated MOSFETs are being immediately written off, post fabrication, due to extrinsic device failures (a.k.a. infant mortality) that originate from the gate oxide. This is essentially another reliability issue, but one that is caught early, with devices failing due to imperfections in this critical layer.
Such is the problem, that every finished device must be tested post-fabrication to catch all the devices that will suffer immediate failure. Unthought of in silicon processing given so few failures, the SiC industry is increasingly turning to burn-in testing, a method in which up to 18 fully-processed SiC wafers are loaded into a chamber and each device on the finished wafer is tested in parallel. These tests entail stressing the device (applying a voltage to the gate) for 48-96 hours to cause those with those that will immediately fail. With this knowledge, the IDMs can eliminate the bad die on the wafer prior to dicing and further packaging or module development.
The cause of extrinsic gate oxide failures is of some continued debate in the industry. Chief among the suspects are the high electric fields in SiC and the lower potential barrier between SiC and SiO2. However, the presence of defects in the oxide is an ever-present touch point for the theories and models that seek to explain gate oxide failures.
Summary
Today’s nitrogen-based oxide processing has taken SiC device fabrication a long way from the poor interface and its low mobility first identified in the early 1990’s. Now adequate in terms of efficiency, the industry has developed ways to deal with the connected yield and reliability issues. What has emerged has been good enough to underpin an automotive qualified product portfolio that is transforming the face of electric vehicle power supplies. Yet, we can still strive for better, a solution that could improve yield, long term reliability and efficiency in a stroke is by tackling the root cause carbon problem.
In part two of this review, we shall look in more detail at the coping strategies and methods used by device designers to manage the challenging oxide. These will include the current industry trend to trench devices, smaller cell pitches, and the protection provided to the gate oxide with these architectures. We shall also consider more radical approaches, including efforts to replace the thermal oxidation process altogether, potentially driving cost reductions across the board.
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